As is commonly known and appreciated, operational amplifier (“op-amp”) integrator circuits, such as the circuit 100 shown in FIG. 1A, are often formed with a resistive-capacitive (RC) feedback loop. As shown, such op-amp circuits commonly include an op-amp (A) 101 having a non-inverting (+) input 102, connected to a reference voltage signal source 104 providing a reference voltage signal VREF, and an inverting (−) input 106, connected to an RC circuit formed by a resistor 103 having a first resistance R1 connected to an input voltage signal source 108 providing an input voltage signal VIN. The inverting input 106 is also connected in parallel with a first capacitor 105 having a first capacitance C1 connected to an output voltage node 110, providing an output voltage signal VOUT of the op-amp 101.
As is commonly known, during operation op-amp circuits will often saturate, resulting in the RC feedback loop being out of regulation. Recovery from saturation often takes time because the op-amps often include a Miller capacitor that requires proper biasing. Further, re-biasing of the capacitor often occurs slowly such that the op-amp circuit 100 itself can be slow to recover. A delay in linear operation of the op-amp 101 commonly arises due to the need for the op-amp 101 to exit clamping and re-bias itself. Re-biasing occurs when the input voltage signal VIN returns to the value of the reference voltage signal VREF. The RC time constant formed by first resistance R1 and first capacitance C1 typically dictates the amount of time needed for the op-amp 101 to resume operating linearly. As used herein, the response of an op-amp circuit in recovering from a saturation and/or clamped output situation is determinable in view of the product of the RC time constant. A recovery that is substantially less than the RC time constant is herein defined to be one that is less than percent (20%) of the RC time constant and such a response is further defined herein as being a “quick” response.
As shown in FIG. 1B, one commonly available solution used to attempt to preventing saturation of the op-amp circuit 100 is to use a “clamping” circuit 111, where the output voltage VOUT of the op-amp circuit 111 is clamped at a maximum output voltage. As shown, often a buffer 112 which includes a device AØ is connected to a clamping voltage signal source 114, which provides a clamping voltage signal VCLAMP. The buffer 112 is further connected in a maximum limiter configuration to the positive supply voltage terminal 116 for the op-amp 101, with the negative supply voltage terminal 118 being connected to a low voltage potential N, such as a grounded voltage potential. VCLAMP is commonly set at a pre-defined value to prevent the op-amp 101 from being driven to too high or low of an output voltage VOUT.
As shown in FIG. 1C, this approach commonly results in a voltage response by the op amp 101 that will incur a delay tdelay in decreasing the output voltage VOUT after the designated value for the clamping voltage signal VCLAMP has been reached. This delay arises because, while the output voltage is clamped, the potential at the negative supply voltage N will drift downwards until the next input voltage signal VIN is received. Further, due to the need for the op-amp 101 A to re-bias, by having the negative input supply voltage N equal the reference voltage VREF, the delay tdelay occurs.
Similarly, other known approaches at preventing saturation of an op-amp integrating circuit by use of clamping or otherwise also suffer from post-clamping recovery delays. Accordingly, a need exists for devices, circuits, and methods which facilitate clamping of output voltages of operational amplifiers, such as operational amplifier integrating circuits, while minimizing post-clamping recovery delays. The various embodiments of the present disclosure satisfy these and other needs.